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> Lattice GAL20RA10B-15LP high speed asynchronous pld
Lattice GAL20RA10B-15LP high speed asynchronous pld
HIGH PERFORMANCE E2CMOS TECHNOLOGY
7.5 ns Maximum Propagation Delay
9 ns Maximum from Clock Input to Data Output
UltraMOS Advanced CMOS Technology
50% to 75% REDUCTION IN POWER FROM BIPOLAR
High Speed Electrical Erasure (<100 ms)
Independent Programmable Clocks
Independent Asynchronous Reset and Preset
Registered or Combinatorial with Polarity
Full Function and Parametric Compatibility with PAL20RA10
PRELOAD AND POWER-ON RESET OF ALL REGISTERS
Standard Logic Consolidation
Multiple Clock Logic Designs
ELECTRONIC SIGNATURE FOR IDENTIFICATION
The GAL20RA10 combines a high performance CMOS process with electrically erasable (E2) floating gate technology to provide the highest speed performance available in the PLD market. Lattice Semiconductor s E2CMOS circuitry achieves power levels as low as 75mA typical ICC which represents a substantial savings in power when compared to bipolar counterparts. E2 technology offers high speed (<100ms) erase times providing the ability to reprogram, reconfigure or test the devices quickly and efficiently. The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell (OLMC) to be configured by the user. The GAL20RA10 is a direct parametric compatible CMOS replacement for the PAL20RA10 device. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacturing. Therefore, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. In addition, 100 erase/write cycles and data retention in excess of 20 years are specified.
The device is a 24-pin Dual-In-Line package.
